1. Field of the invention
This invention relates to a sampling signal generation circuit in which the most suitable signal can be generated so as to carry out a correct sampling of an input signal.
2. Description of the prior arts
In a circuit for sampling digital signals, e.g., data signals, according to a synchronizing signal, e.g., a clock signal, these digital signals should be input in a stable and effective state. The circuit includes a sampling circuit for separately sampling output signals from a flip-flop circuit. In order to realize said stable sampling, clock signals should not be given when signals to be sampled are in an unstable state or in a transition state.
In the past, to realize said stable sampling, the length of signal lines, in which sampling signals and clock signals are traveling, were so adjusted that timings between both signals become appropriate. In other words, the traveling speeds of signals to be sampled and clock signals were adjusted by changing their signal line lengths. In this case, however, the signal line lengths should be decided precisely by correctly calculating the traveling delays of signals in the circuit, so as to obtain an appropriate timing between both signals. This means that an enormous effort was required to design circuits correctly. Furthermore, as traveling speeds of signals become faster, flexible period of timings between both signals becomes shorter. The signal line lengths should, therefore, be decided more precisely, thus making it a difficult to design such circuits.
Once the circuit, which is designed as mentioned above, is fabricated as an integrated circuit product, errors arise between real circuit values of the product and designed values, due to various reasons which are caused within fabrication processes. If these errors are above the tolerance, an additional adjustment, such as to form a signal line using a concentric cable outside a chip, is required to correct the errors. Because of this adjustment, however, the integration of the circuit become difficult, thus causing difficulty in reducing the size of a product.
In addition to the disadvantages mentioned above, the prior art circuit has another disadvantage. That is, when the phase of a sampling signal, which is synchronous with a clock signal, varies during the operation, there is no way to correct the timing of both signals to avoid an erroneous operation. In other words, the prior art circuit cannot carry out real time processing for the phase variations of a sampling signal and a signal to be sampled. As a result, the reliability of the prior art circuit is degraded.